A graphic representing the physical structure of Gate All Around (GAA) technology on the left, a next-generation transistor structure renowned for its power efficiency, and on the right a chart of the comparative operation voltages of different types of semiconductor designs: Planar, FinFET, and GAA.
A graphic representing the physical structure of Gate All Around (GAA) technology on the left, a next-generation transistor structure renowned for its power efficiency, and on the right a chart of the comparative operation voltages of different types of semiconductor designs: Planar, FinFET, and GAA.

In the intensifying battle of foundry services (semiconductor contract manufacturing), Taiwan’s TSMC has confidently affirmed its technological prowess.

According to industry sources on Oct. 23, C.C. Wei, CEO of TSMC, responded with a firm “no” when asked during a recent conference call for the Q3 (July-September) financial results whether they anticipate losing market share due to Intel’s entry into the foundry market.

He stated, “Based on our internal assessments, the N3P technology exhibits a PPA (three main semiconductor indicators: performance, power, and area) comparable to a competitor’s 18 A technology, but with faster rollout and higher technological maturity.” He emphasized that it also “offers significantly lower costs.” The N3P process, an improvement over the current N3, enhances performance, semiconductor integration, and power consumption. It’s expected to be introduced next year.

Regarding the 3-nanometer (nm) technology currently used in the production of the Apple iPhone’s mobile application processors, TSMC mentioned, “It will account for a mid-single-digit percentage of our total wafer sales this year.” They further added, “Next year, due to robust demand from various clients, we expect a much higher proportion.”

The percentage of TSMC’s Q3 sales from the 3-nm process stands at around 6%. The company also disclosed continuous advancements in 3-nm technologies, including N3E, which is slated to start mass production in Q4 (October-December) of this year, along with N3P and N3X.

CEO Wei emphasized the forthcoming 2-nm technology to be launched in 2025, calling it a “process more advanced than N3P or 18 A.” While he did not specifically mention any companies, the remark is interpreted as a nod toward Samsung Electronics, which has announced the mass production of 2-nanometer chips in 2025.

Amid a surge in demand related to artificial intelligence (AI), TSMC anticipates the accelerating need for low-power computing. This in turn is expected to drive increased market demand for 2-nm technology.

In its 2-nanometer process, TSMC plans to adopt Gate All Around (GAA) technology, a next-generation transistor structure renowned for its power efficiency, following Samsung Electronics. TSMC emphasized, “Through our continuous improvement strategy, the 2-nm and its derivative products will further extend our technological leadership into the future.”

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