All about Packaging

The advanced packaging technique called Chip-on-Wafer-on-Substrate
The advanced packaging technique called Chip-on-Wafer-on-Substrate

Global customers have been lining up to buy Nvidia’s graphics processing units (GPUs), but tight supply has sent prices soaring. GPUs are the brains of generative artificial intelligence (AI) programs like ChatGPT. Nvidia commands more than 90 percent of the global GPU market for AI.

The recent rapid development of the AI industry has been fueling global demand for Nvidia’s GPUs, but they are still in short supply. Nvidia’s flagship A100 and H100 GPUs, famous for their use for ChatGPT, are entirely outsourced to TSMC. In early June, TSMC decided to scale up its packaging capacity at Nvidia’s request.

TSMC can exclusively roll out Nvidia chips thanks to its packaging technology called Chip on Wafer on Substrate (CoWoS). Chips for AI that process data quickly and efficiently are technically challenging and require an advanced packaging technology. The importance of packaging technology as a way to boost the performance of semiconductors has been emphasized as ultra-micro fabrication processes recently reached their limits at two hundred thousandths of the thickness of a human hair.

In the packaging process, chips are stacked three-dimensionally in a single thin film so the distances among them are reduced. This makes connections among chips faster, leading to huge performance gains of up to 50 percent or more. How the chips are stacked and packaged makes a huge difference in performance.

TSMC first introduced CoWoS technology in 2012 and has continued to upgrade its packaging technology since then. In the meantime, the global semiconductor industry saw the emergence of a new technology that combines different types of semiconductors, such as memory and system semiconductors, to create entirely new classes of semiconductors (heterogeneous integration). Now, Nvidia, Apple, and AMD cannot make their core products without TSMC and its packaging technology.

This means that Nvidia can get its hands on finished chips by relying on TSMC for packaging as well as foundry work.

In other words, foundry service users will pay attention not only to how well a foundry company can manufacture chips but to how well it can package those chips after making them. TSMC has other packaging technologies besides CoWoS. In addition to TSMC, Taiwanese semiconductor packaging specialists have already dominated the global market. Including ASE, the world’s No. 1 company in this field, Taiwanese companies have a 52 percent share of the global packaging market.

This unrivaled packaging technology explains why global IT giants such as Nvidia and Apple still want to use TSMC’s production lines even though Samsung Electronics succeeded in mass-producing 3-nm semiconductors ahead of TSMC in 2022. As a result, all big foundry orders for AI and autonomous driving semiconductors have gone to TSMC, and the market share gap is getting wider and wider between that company and Samsung. TSMC showed its intentions to definitely win its competition with Samsung when it started the operation of Fab 6, a semiconductor production plant that specializes in high-end packaging, on June 8.

Samsung has also launched an all-out effort to develop advanced packaging technology that will take chip performance to the next level. At the Samsung Foundry Forum 2023 held on June 27, Samsung Electronics announced an all-out packaging war with TSMC, saying that it will not only advance its packaging technology but also grow related ecosystems. To this end, the Korean semiconductor giant even introduced the concept of a one-stop packaging service. It plans to provide customized packaging services for customers that want to improve the performance of their chips. In the long term, it will create a new line dedicated to packaging.

In order to overtake TSMC’s CoWoS, Samsung is also developing a more advanced concept of I-cube and X-cube packaging technologies. In particular, the Korean chipmaker is reportedly focusing its research on three-dimensional (3D) packaging in which multiple chips are stacked vertically to boost performance. “Samsung is preparing a more advanced way, the three-dimensional packaging of semiconductors,” a semiconductor industry insider said. “Soon there will be a head-on collision between Samsung and TSMC in packaging.”

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