Chip Competition
The focus of the competition among memory semiconductor manufacturers is shifting from microfabrication to lamination, as microfabrication techniques for reducing the circuit line width reach the structural limit of 14 nanometers. Under the circumstances, it is expected that the finesse of vertical memory cell stacking will be the key to successful business.
Samsung Electronics recently finished the development of a 14.3-nanometer NAND flash memory device and adjusted the microfabrication goal to 14.2 nanometers. In the semiconductor industry, the nanometers regularly talked about measure how wide the circuit line is. The shorter the width, the higher the performance and the lower the production cost. Global semiconductor companies have increased their investment in microfabrication technology with this goal in mind.
At present, Samsung Electronics is manufacturing 20 nm chips when it comes to DRAM. The NAND flash process has been refined from 40 nm to 16 nm since the mid-2000s. Industry experts consider 14 nanometers to be the final stage of microfabrication, because 10 nm NAND flash chips, although technically feasible, are not profitable in view of the required equipment investment.
The reduction of the circuit line width for smaller and finer chips allows more chips to be produced per wafer. However, it narrows the gap between the cells as well, which can cause interference and instability. Samsung Electronics’ target correction by just one-tenth of a nanometer has to do with this limitation.
This is why an increasing number of companies are trying to make a breakthrough with 3D semiconductor devices, in which cells are stacked vertically. 3D chips are particularly advantageous in terms of capacity, durability, and power efficiency.
It is Samsung Electronics that has the most advanced cell stacking technology. It was the first to announce the mass production of 24 layer 3D V NAND flash memory in August last year, and released the world’s first 32-layer V NAND product in May this year. Some experts predicted that the company has already completed the development of a 48-layer prototype. In addition, it released through silicon via (TSV)-based 3D DRAM on August 27.
Toshiba is also increasing its investment in 3D NAND. It is planning to set up additional manufacturing facilities for the purpose by 2016 and produce 40 to 70 layer V NAND in the near future. SK Hynix is going to start the mass production of 3D NAND within this year, too. Insiders are estimating that the number of layers could reach 100 within a few years.