Boding Well for Equipment Makers
The authors are analysts of NH Investment & Securities. They can be reached at kyuha.lee@nhqv.com, hwdoh@nhqv.com and j.ko@nhqv.com, respectively. – Ed.
Demand has been on the rise as of late for high-performance computing for computations that cannot be solved by conventional computing resources. To solve this issue, it is essential to increase bandwidth by connecting heterogeneous semiconductors in 3D packaging. This trend is more positive for back-end process equipment makers than front-end players. Related domestic companies include Hanmi Semiconductor, Park Systems, and EO Technics, while overseas players include Lasertec.
Wire bonding, flipchip, and WLP are conventional semiconductor packaging technologies
There are four semiconductor packaging technologies: wire bonding, flip-chip, wafer-level packaging (WLP), and through-silicon via (TSV). Around 80% of today’s packages are based on wire bonding, which is an older technology. Wire bonding is the process of creating electrical interconnections between semiconductors (or other integrated circuits) and silicon chips using bonding wires, which are fine wires made of materials such as gold. Flip-chip and WLP are more advanced approaches. In flip-chip, copper bumps are formed on top of a chip using different type of equipment. The device is flipped and mounted on a separate die or board. WLP, meanwhile, packages the dies while in a wafer-like format.
TSV represents most advanced technology
Among the four semiconductor packaging technologies, TSV is the most advanced technology that can be used for high volume manufacturing. TSV is a vertical electrical connection that passes completely through a silicon wafer or die. Connections between layers are created by etching via holes. In HBM2, TSV enables eight to twelve dies to be stacked. TSV minimizes die size to 50μm and hole size to 4μm.
Hybrid bonding coming under limelight
Recently, semicon manufacturers such as TSMC and SEC have developed 3D IC packaging technologies, namely SoIC and X-Cube. While the performance of conventional 3D packaging technology is limited by low bump density, 3D IC packaging technologies enable sub-10μm bonding pitches using copper hybrid bonding, which allows for 10,000 bumps/1mm2. Copper hybrid bonding first appeared in 2016, when Sony used the technology for CMOS image sensors via the licensing of Xperi’s Direct Bond Interconnect (DBI).
Hybrid bonding typically performed in front-end processes
While conventional packaging technologies have mainly been used in back-end operations, hybrid bonding processes (used in advanced packaging technologies) are mostly conducted in the front-end process—this means that separate manufacturing facilities are required for hybrid bonding to be performed at back-end fabs. Given that the construction of such facilities requires massive investment, we believe that it will be impossible for back-end manufacturers to conduct hybrid bonding over the near term.
Hybrid bonding process
Hybrid bonding is carried out in the following order: 1) tiny vias are patterned and etched on wafers for electrical connection; 2) the vias are then filled with copper using a CVD process to form copper pads on the surface of the wafers; 3) the surface of the wafers are polished using CMP; and 4) during the CMP process, the copper pads are slightly recessed on the surface of the wafer, creating about 10μm bump pitches for the vertical electrical connections.
Hybrid bonding to spur demand for more advanced CPM, AFM, dicing, and flip-chip bonder
Then, the wafers undergo a metrology step, which measures and characterizes the surface topography using AFM. Once surface structures are measured, the wafers undergo a cleaning and an annealing process. Then, the chips are diced on the wafer using a blade or laser dicing system, creating individual dies for packaging. We note that as the size of pads continues to get smaller, making them more sensitive to tiny particles, demand for laser dicing machines is predicted to increase going forward. We also expect the semicon industry to consider introducing plasma dicing technology in the future. Next comes the bonding step. A flip-chip bonder is used to pick up the die directly from a dicing frame. Then, the die is placed onto a host wafer or another die. All in all, we predict that wider application of hybrid bonding for chip packaging will boost demand for more advanced CPM, AFM, dicing, and flip-chip bonder systems.
TSMC and Intel unveil their own hybrid bonding technologies
TSMC is currently developing system on integrated chip (SoIC) technology, a 3D IC inter-chip stacking technology that allows for the integration of chiplets with multiple layers, sizes, and functions. Accordingly, SoIC offers greater functionality versus 2D stacking technology. With process validation already completed, mass production for SoIC is expected to begin in 2021.
SoIC fully compatible with existing advanced packaging services
Of note, the performance of conventional 3D packaging technology is limited by low density bonding. But, TSMC’s SoIC enables sub-10μm bonding pitches using copper hybrid bonding, which allows for 10,000 bumps/mm2. Also positive, the technology is fully compatible with existing advanced packaging services, such as chip on wafer on substrate (CoWoS) and integrated fan-out WLP (InFO).
Intel unveiled hybrid bonding technique at 2020 Architecture Day
Intel unveiled its next-generation packaging technologies at 2020 Architecture Day. So far, the firm has been applying its in-house-developed 2.5D and 3D packaging technologies (embedded multi-die interconnect bridge (EMIB) and Foveros) for chip manufacturing. Intel’s next-generation packaging technology also uses copper hybrid bonding, just like TSMC’s SoIC. According to the company, its hybrid bonding is to greatly increase bump count (up to 16,000/mm2), which in turn should allow for a significant reduction in power consumption to 0.05 picojoules per bit. We note that bump count currently stands at about 400 for EMIB and 1,600 for Foveros.
ODI to resolve heating issue
Intel claims that hybrid bonding will enable the creation of smaller and simpler circuits and the lowering of capacitance. While advancement in packaging technology entails heating issues, Intel says that omni-directional interconnect (ODI) will be used to resolve such problems. ODI allows top-level chips to overhang lower-level chips, thus eliminating some regions of TSV. As TSV die areas shrink, direct power delivery to the top die (which consumes proportionately more power) becomes possible.
SEC unveils X-Cube technology
On Aug 13, SEC unveiled its X-Cube 3D packaging technology. Built on 7nm technology, the X-Cube test chip uses TSV to stack SRAM on top of a logic die, freeing up space to pack more memory into a smaller footprint. X-Cube enables significant leaps in speed and power efficiency to help address the rigorous performance demands of next-generation applications such as HPC, AR/VR computing, and mobile/wearable goods.
X-Cube differs from other packaging technologies in elimination of intermediary interposers and silicon bridges
X-Cube is different from existing 2.5D and 3D packaging technologies in that it does away with intermediary interposers and silicon bridges, and directly connects a stacked chip on top of a primary logic die. TSMC’s 2.5D technology connects HBM with a logic die through silicon interposers. In X-Cube, however, the logic die is designed with TSV pillars, which then connect to μ-bumps with only 30μm pitch, allowing the SRAM-die to directly connect to the main die without intermediary mediums. SEC has completed the development of a 7nm EUV process based on X-Cube. If next-generation packaging technologies are used for high volume manufacturing, SEC’s X-Cube should prove better than its counterparts in terms of speed and cost.
Cerebras Systems’ WSE: Good example of leading-edge post-fab technology utilization
As a good example of a chip using leading-edge post-fab technology, Cerebras Systems’ recently-announced Wafer Scale Engine (WSE) is garnering strong market attention. The WSE is packed onto a single 215mm x 215mm chip manufactured on a TSMC 300mm wafer using a 16nm process.
WSE 57x larger than Nvidia’s V100
The WSE features 400,000 AI-optimized cores, which are programmable, ensuring that they can continue to run neural network algorithms in the constantly changing field of deep learning. Capable of performing arithmetic, logical, branching, and tensor operations, the WSE is 57x larger and has 3,000x greater capacity, 10,000x greater bandwidth, and 78x more cores than Nvidia’s V100.
Cerebras Systems partners with TSMC
On the WSE, all cores are interconnected using a uniform 2D mesh fabric with an emphasis on low latency for local communication. Communication is conducted entirely via hardware, eliminating any software overhead. This fabric is not only used for intradie communication but for inter-die connections. Of note, Cerebras Systems has partnered with TSMC to develop better inter-die connections. Together, the firms repurposed the scribe lines—the mechanical barriers between two adjacent dies, which are typically used for test structures and eventually for ‘strangulation’. With the help of TSMC, the metal deposition was extended across the scribe lines, enabling Cerebras Systems to seamlessly extend the 2D mesh across dies. With no external memory, the whole of the WSE’s memory is fully distributed across the cores of the on-chip SRAM, similar to a large NPU with a big cache. As it is all on-die, the performance boost from the core not having to communicate with external memory is significant.
Cerebras Systems solved problems of: 1) high manufacturing costs; and 2) chip-generated heat
There are two common problems for large chips like the WSE, however. First, manufacturing costs are high, given that even a single defect within a die can impact the entire chip. To address this issue, Cerebras Systems uses both redundant cores and redundant fabric links. Each wafer incorporates around 1~1.5% of additional AI cores for redundancy reasons. In an area affected by a defect, a local redundant core is used to replace the defective core. The local fabric is then reconnected using redundant fabric links. The second problem is heat generation. To address this stumbling block, Cerebras Systems designed a custom connector sandwiched between the silicon wafer and PCB. It also chose to go vertical; cold water carries heat from the cold plate directly out of the package perpendicular to the wafer. The two techniques enable highly uniform distribution of both power and cooling, including at the edges and within the wafer.