Chiplet to See Full-scale Application
The author is an analyst of NH Investment & Securities. He can be reached at hwdoh@nhqv.com. -- Ed.
At ISSCC 2020, attention focused on chiplet technology, which can overcome many limitations of micro processing. Chip architecture design and packaging technology are to be highlighted going forward.
Attention turns to AMD architecture at ISSCC 2020
At the 2020 International Solid-State Circuits Conference (ISSCC; the world’s most prestigious semiconductor conference; held over Feb 16~20), this year’s semiconductor technology trends were on display. At the conference, papers on machine learning, quantum computing, 5G RF connectivity, etc, drew attention. Meanwhile, focus also turned to the Zen2 CPU core and chiplet technologies that AMD has put into production since 2019.
The main interest regarding Zen2 technology lies in its introduction of the 7nm process for the first time in manufacturing, an innovation that improved performance by 15% versus the previous process. Compared with the original circuit’s 10-track cell library, Zen2 used a 6 track cell library - a significant change. We note that reducing the number of cell library tracks in logic semiconductor design is an achievement of the highest difficulty.
Importance of design and package processes rising in line with full adoption of chiplet technology
Also very impressive is chiplet technology, which divides a processor consisting of one die into multiple dies and then connects the dies together. While Intel had been negative towards the technology in the past, AMD has gained a technological edge via full-scale adoption (from 2019) of chiplet technology. The chiplet technology adopted in Zen2 architecture is named Core Complex Die (CCD). In detail, CCDs corresponding to CPU cores are manufactured using a 7nm process, and peripheral dies are manufactured at a 14nm process. This approach lowers the production costs for manufacturing all the supportive parts of the chip, rather than just manufacturing them all at 7nm. AMD solves the performance penalty from die-to-die connectivity by connecting dies with a technology called Infinity Fabric On-Package (IFOP). Although boasting superior performance, Silicon Interposer-based technology has not been adopted due to its heftier price tag.
The key takeaway of chiplet technology is a slowing in logic chip process migration. Only the necessary parts are introduced in the latest process, and the unnecessary parts are manufactured in the old process and connected through the chiplet technology, thereby achieving high performance. Moving ahead, we believe that the importance of architecture design, back-end, and packaging processes will be more important than the development of front-end process.