The author is an analyst of NH Investment & Securities. He can be reached at email@example.com. -- Ed.
In 2020, new memory capacity investment is expected to increase sharply, following a dip in 2019. Also positive for the semicon equipment industry are the trends of expanding logic chip sizes (driven by competition among logic semicon makers) and rising demand for new equipment on the start of EUV lithography mass production.
2020 outlook: Memory equipment investment to increase
Memory equipment investment is expected to increase in 2020 in response to a decline in investment in 2019. Considering recent improvement in memory supply-demand conditions, a significant memory supply shortage is likely in 2021 unless investment picks up in 2H20. Accordingly, we expect major memory makers to ramp up investment in 2H20. In 2020, we forecast memory capacity expansion at Samsung Electronics (SEC) at 50K wpm for DRAM and 85K wpm for NAND, with capacity expansion at SK Hynix at 30K wpm for DRAM. Given these estimates, major memory front-end equipment makers have the potential to record their strongest-ever earnings in 2020.
Increasing chip sizes and introduction of EUV into DRAM process to also benefit equipment industry
Driven by competition among logic chipmakers, the size of logic chips is on the rise. Based on a fixed capacity, chip shipments should decline as chip sizes increase—a factor which should drive up capacity investment. In 2020, Intel is to invest US$17bn to boost its capacity by 25% y-y. TSMC plans to make a US$15bn investment, which is 50% higher than its 2018 level.
As evidence of increasing chip sizes, we draw attention to the wafer scale engine (WSE) chip developed by startup Cerebras Systems. Representing an extreme increase in chip size to boost AI computational power, the WSE is the same size as one wafer; it is manufactured on a 300mm wafer from TSMC.
The introduction of EUV equipment for the 5nm logic and 1znm DRAM processes should benefit the semicon equipment industry. We note that TSMC is introducing EUV for 4~5 layers, including at 5nm EUV lithography for 32nm pitch M2 layers, 36nm pitch contacts, hole arrays, etc.
The challenge presented by tech-migration has risen sharply as of late, particularly starting with 1znm and below DRAM, for which capacitor shape is changed to a pillar. For smooth 1znm migration, EUV equipment is to be applied to 1~2 layers, including bitline contacts. In order to introduce EUV lithography equipment to mass production, EUV-tailored mask, pellicle, photoresist, gas supply equipment, and testing equipment will need to be developed and installed. We view this as positive for the overall semicon equipment industry.