Samsung Electronics announced on Oct. 7 that it has developed the world’s first 12-layer 3D through silicon via (TSV) technology for cutting-edge semiconductor packaging, which is to allow signal transmission to and from a semiconductor chip and protect the chip from external shocks during chip mounting onto a substrate or an electronic device.
The technology developed by Samsung Electronics is characterized by 12 DRAM chips being vertically stacked and connected with each having a thickness equivalent to half of the thickness of paper. At present, it is the most precise and challenging semiconductor packaging technology.
“With the new technology, it is possible to stack 12 DRAM chips while maintaining the same package thickness as existing 8-layer HBM2 products, that is, 720 micrometers,” Samsung Electronics explained, adding, “Clients will be able to release next-generation high-capacity and high-performance products even without any change in system design.”
These days, Samsung Electronics is concentrating its resources on semiconductor packaging in particular. This is based on a conclusion that proactive competitiveness enhancement in that field is becoming increasingly necessary with semiconductor products used for artificial intelligence, autonomous driving, mobiles, and so on improving in performance and decreasing in size at a rapid pace.