64-Layer 3D NAND

Western Digital (WD) has unveiled a 4-bit per-cell flash memory architecture using a 64-layer 3D NAND quadruple-level cell (QLC) technology.
Western Digital (WD) has unveiled a 4-bit per-cell flash memory architecture using a 64-layer 3D NAND quadruple-level cell (QLC) technology.

 

Western Digital (WD) recently unveiled a 4-bit per-cell flash memory architecture based on BiCS3 which is a 64-layer 3D NAND quadruple-level cell (QLC) technology.

WD's BiCS3 QLC technology provides single-chip storage of 768 Gb, a 50 percent improvement over existing TCL architecture-based 512 Gb chips. This technology will be commercialized in various forms such as SSDs and removable memories according to characteristics of various environments requiring high capacity storages demanded by individuals and companies.

It is expected that the technology to be loaded into next-generation 3D NAND technology including 96-layer 3D NAND (BiCS4) technology.

Meanwhile, Western Digital will showcase various storage products such as SSDs and removable memories based on BiCS3 X4 and related system technology at the Flash Memory Summit 2017 to be held at the Santa Clara Convention Center in the US in August this year.

 

 

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