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Samsung Electronics Announces World’s First 4-Nano Processing Roadmap
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Samsung Electronics Announces World’s First 4-Nano Processing Roadmap
  • By Cho Jin-young
  • May 26, 2017, 03:00
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Kim Ki-nam, president of the semiconductor business unit at Samsung Electronics, presents the company’s latest foundry processing technology and solutions at the Samsung Foundry Forum held in Santa Clara of the U.S.
Kim Ki-nam, president of the semiconductor business unit at Samsung Electronics, presents the company’s latest foundry processing technology and solutions at the Samsung Foundry Forum held in Santa Clara of the U.S.

 

Samsung Foundry Forum 2017
Samsung Foundry Forum 2017

 

Samsung Electronics Co., which recently separated its foundry business into a new unit to focus on the non-memory chip sector, has announced its 4-nanometer processing roadmap for the first time in the world. One nanometer (nm) is one-billionth of a meter. Accordingly, the company has proved its competitiveness once again by surpassing Taiwan Semiconductor Manufacturing Co. (TSMC), the world's largest chip foundry which announced to develop a 5-nm processing by 2019 early this year. Semiconductor process refining is a key source of competitive edge to improve performance of chips and power efficiency. With Samsung Electronics’ latest announcement of its roadmap, global foundry companies are expected to compete harder to lead technology.

Samsung Electronics hosted the Samsung Foundry Forum in Santa Clara of the U.S on May 24 (local time) and revealed its advanced refining process roadmap from 8 nm to 4 nm and advanced foundry processing, including fully depleted-silicon on insulator (FD-SOI) solution, to 400 officials from foundry customer companies and partner companies. The forum was the first event held by Samsung after the company set up the foundry business unit on the 12th. It was attended by Kim Ki-nam, president of Samsung’s semiconductor business unit, Chung Eun-seung, vice president of the foundry business unit, Yoon Jong-shik, vice president of Samsung Electronics and Bae Young-chang, vice president of Samsung's LSI business unit.

The 4-nm low power plus (4LPP), which was first unveiled by Samsung Electronics during the forum, is a technology that doesn’t exist yet. Until now, there have been a widely-accepted theory that it is impossible to develop a process of less than 5 nm even with “FinFET,” which was developed by Samsung Electronics in 2015 for the first time in the world to enter the existing semiconductor process of less than 20 nm. FinFET, also known as Fin Field Effect Transistor, is a 3D-like structure that has a greater contact area between gate and channel of transistors. However, Samsung Electronics succeeded in developing multi-bridge channel FET (MBCFET), the next-generation transistor structure that surpasses FinFET, and finally presented a plan to complete the 4LPP development by 2020.

In addition to the 4LPP, Samsung Electronics announced its roadmap for advanced processes – 8LPP, 7LPP, 6LPP and 5LPP, giving customer companies a wider range of options. The 8LPP is the most competitive fine process that can be realized without using an extreme ultraviolet (EUV) lithography equipment which costs about 200 billion won (US$178.49 million) per unit. Samsung Electronics is planning to complete the development of processes below 7LPP in stages using the EUV equipment starting from next year.

Furthermore, the company announced to expand the 28-nm FD-SOI technology, which is suitable for the Internet of Things (IoT), and the next-generation 18-nm FD-SOI technology with magnetic random access memory (MRAM). FD-SOI is a technology that reduces leakage currents in cells by forming an oxide film on wafers. The technology is at the center of attention as low-power semiconductor for IoT devices has recently become the talk of the town. MRAM, a non-volatile memory that uses magnetic materials, is 1,000 times faster than flash memory in write speeds.